Systems and methods for ISA support for indirect loads and stores for efficiently accessing compressed lists in graph applications

ABSTRACT

Disclosed embodiments relate to systems and methods for performing instructions to access a compressed graphic list. In one example, a processor includes fetch and decode circuitry to fetch and decode the single instruction to access the compressed graphic list, and execution circuitry to execute the decoded single instruction to cause access to the compressed graphic list by: receiving, from a load store queue, at a first op-engine associated with a first data location, an indirection request, computing, via the first op-engine, a second data location associated with a second op-engine, computing, via the second op-engine, a third data location associated with a third op-engine responsive to the indirection request, and providing, via the third op-engine, a data response to the load store queue responsive to receiving data from the third data location.

FIELD OF INVENTION

The field of invention relates generally to computer processor architecture, and, more specifically, to systems and methods for indirect loads and stores for efficiently accessing compressed lists in graph applications.

BACKGROUND

Large sparse matrices are compressed into a compressed sparse row (CSR) format. The CSR format is a vectorized list of non-zero entries in a sparse matrix. A sparse matrix represented in a CSR format has three 1-D arrays. Before finding the location of interest, each indirect load or store increases performance overheads in that a read of the pre-built neighbor index is performed from the list in memory, the value of the neighbor index is dereferenced to find the location of the value of interest, and a load or store request is sent to that final value.

Supporting indirect loads and stores for efficiently accessing compressed lists in graph applications may assist in meeting the needs of processors, for example, by providing the ability to combine multiple operations into a single instruction which lowers the total latency and increases code efficiency.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and are not limitations in the figures of the accompanying drawings, in which like references indicate similar elements and in which:

FIG. 1 illustrates a block diagram of a pipeline indirection system architecture based on a multi-indirection according to one embodiment of the invention;

FIG. 2 illustrates a block diagram of a pipeline indirection system based on a single-indirection according to one embodiment of the invention;

FIG. 3 illustrates examples of embodiments of a method of accessing a compressed graphic list as detailed herein;

FIG. 4 illustrates a table showing instruction definitions for three operations according to some embodiments detailed herein;

FIG. 5 illustrates an example pseudo-code to execute a double-indirect load according to one embodiment of the invention;

FIG. 6 illustrates an example base+offset address format according to one embodiment of the invention;

FIGS. 7-8 are block diagrams illustrating a generic vector friendly instruction format and instruction templates thereof according to embodiments of the invention;

FIGS. 9A-D illustrate an exemplary specific vector friendly instruction format according to embodiments of the invention;

FIG. 10 is a block diagram of a register architecture according to one embodiment of the invention;

FIG. 11A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments of the invention;

FIG. 11B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments of the invention;

FIGS. 12A-B illustrate a block diagram of a more specific exemplary in-order core architecture, which core would be one of several logic blocks (including other cores of the same type and/or different types) in a chip;

FIG. 13 is a block diagram of a processor 1700 that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the invention;

FIGS. 14-17 are block diagrams of exemplary computer architectures; and

FIG. 18 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

The pipeline indirection system is a system to access a list data structure, a compressed list in a graph application (e.g., a compressed graphic list), or any other suitable list. The compressed list may be accessed via an indirection request. As used herein, the term “indirection request,” may be used to refer to a request to access a compressed list in a graph application that includes an indirect load operation, indirect store operation, and/or a store acknowledgement.

Supporting indirect loads and stores for efficiently accessing compressed lists as described herein provides for performance improvements by combining multiple operations into a single instruction and supporting remote address computation which increases code efficiency. Further, supporting indirect loads and stores as described herein eliminates round-trip latencies for each memory access while reducing per-operation latency.

For example, a pipeline indirection system starts with fetching and decoding, a single instruction to access a compressed graphic list. The compressed graphic list is accessed by receiving an indirection request, from a load store queue, at a first op-engine associated with a first data location. A second data location associated with a second op-engine is computed via the first op-engine. A third data location associated with a third op-engine is computed via a second op-engine and a data response is provided to the load store queue responsive to receiving data from the third data location.

FIG. 1 illustrates a block diagram of a pipeline indirection system architecture with a multi-indirection according to an embodiment of the invention. As shown, the pipeline indirection system 100 includes a pipeline 102 communicably and operatively coupled to a load store queue (e.g., LSQ 105), one or more op-engines (e.g., the Op-engines 110, 120, and 130), one or more data locations (e.g., the Data Locations 115, 125, and 135), and one or more additional systems, components, etc. It should be understood that the pipeline indirection system 100 may include additional, less, and/or different components/systems than depicted in FIG. 1, such that the principles, methods, systems, processes, and the like of the present disclosure are intended to be applicable with any other pipeline indirection system configuration. It should also be understood that the principles of the present disclosure contemplates that the principles may also be applied to a variety of other applications.

As shown, the pipeline indirection system 100 includes the pipeline 102. A single instruction (e.g., a load.ind instruction, store.ind instruction, etc.) is issued to the pipeline indirection system 100 at the pipeline 102. In some embodiments, an indirection level may be determined for the indirect load operation and/or the indirect store operation. The indirection level may be to indicate a multi-level indirection (e.g., a double indirection) or a single level indirection (e.g., a single indirection). If the indirection level (e.g., the LEV-IND modifier) is set to 1, an indirection request (e.g., an indirect-load or indirect-store request) may be provided to at least two data locations (e.g., next list locations) which then dereferences the address of the final data location as described herein.

In this regard, the LSQ 105 issues a single instruction that includes an indirection request (e.g., a double indirection such as an IND-IND-LD packet) to the Op-engine 110. As used herein, the term “Load Store Queue (LSQ),” may be used to refer to a queue to store data and/or information associated with one or more instructions. In some embodiments, the data stored in the LSQ 105 may be passed or otherwise provided between instructions, one or more op-engines, (e.g., the Op-engine 110, 120, 130, etc.), or any other suitable component(s). The op-engine (e.g., the Op-engine 110) may be located near the list memory.

The indirection request may instruct the Op-engine 110 to retrieve a first pointer from the Data Location 115. As used herein, the term “data location” may be used to refer to scratchpad memory, double data rate (DDR) memory, or any other suitable storage location. The first pointer from the Data Location 115 may be utilized to determine the location of a second pointer.

In turn, the Op-engine 110 may compute or otherwise determine the next pointer location (e.g., a register such as r3 as referenced herein in the table of FIG. 4). For example, the Op-engine 110 may determine that the next pointer location is the Data Location 125 associated with the Op-engine 120. The Op-engine 110 may send, pass, or otherwise provide an indirection request to the Op-engine 120. For example, the Op-engine 110 may send or otherwise provide the indirection request (e.g., an IND-LD packet) to the Op-engine 120. In some embodiments, the Op-engine 110 may generate an indirection request (e.g., a second indirection request such as, but not limited to, an IND-LD packet) for provision to the Op-engine 120. The indirection request may include a second register such as r4 (as described herein with reference to FIG. 4) to compute the pointer at the Data Location 125.

At the Data Location 125, the Op-engine 120 may retrieve a pointer from memory and perform a pointer computation using the register value to determine that the next pointer location is the Data Location 135. The op-engine 120 then sends an indirection request (e.g., an Op-load request) to the Data Location 135, which is retrieved or otherwise received by the Op-engine 130 at the Data Location 135.

The data is read responsive to the indirection request by the Op-engine 130 from the Data Location 135 and a data response (e.g., a data value, data acknowledgement, or a combination thereof) is provided (e.g., sent) to the LSQ 105.

FIG. 2 illustrates a block diagram of a pipeline indirection system architecture according to one embodiment of the invention. A single instruction (e.g., a load.ind instruction) is issued to the pipeline indirection system 100 at the pipeline 102. The LSQ 105 issues the single instruction that includes an indirection request (e.g., a single indirection such as an IND-LD packet) that is provided to the Op-engine 210. If the indirection level (e.g., the LEV-IND modifier) is set to 0, a store or load is provided to a data location (e.g., a dereferenced location such as the Data Location 215 and/or 225) and a data response (e.g., a data value, data acknowledgment, or a combination thereof) is returned to the LSQ 105.

Accordingly, the Op-engine 210 may receive the indirection request (e.g., an IND-LD packet). At the Data Location 215, the Op-engine 210 may retrieve a pointer from memory and perform a pointer computation using the register value to determine that the next pointer location is the Data Location 225. In turn, the Op-engine 210 may send or otherwise provide the indirection request to the Op-engine 220. For example, the Op-engine 210 may send or otherwise provide an indirection request (e.g., an Op-load request) to the Data Location 225, which is retrieved or otherwise received by the Op-engine 220 at the Data Location 225.

The data is read responsive to the indirection request by the Op-engine 220 from the Data Location 225 and a data response (e.g., a data value, data acknowledgement, or a combination thereof) is provided (e.g., sent) to the LSQ 105.

FIG. 3 illustrates examples of embodiments of a accessing a compressed graphic list. FIG. 3 is triggered responsive to an instruction (e.g., a load.ind instruction) issued to the pipeline. The processing of the method is performed by components of a processor or core including, but not limited to, the processors as detailed herein.

FIG. 3 illustrates an embodiment of a processor executing a single instruction to access a compressed graphic list. At 301, the processor is to fetch, using fetch circuitry, a single instruction. The single instruction includes at least one of a list load, pointer deference, an indirect load operation, or an indirect store operation. Advantageously, the inclusion of multiple operations (e.g., a list load, pointer deference, an indirect load operation, or data load/store) into a single instruction, increases code efficiency and reduces per-operation latency by supporting remote address computation and eliminating round-trip latencies for each memory access.

The fetched single instruction is decoded. For example, the fetched single instruction is decoded by decode circuitry such as that detailed herein. The execution of the decoded single instruction is to cause access to the compressed graphic list by receiving an indirection request. The indirection request includes an indirect operation. The indirect operation may include an indirect load operation or an indirect store operation. In some embodiments, an indirection level may be determined for the indirect load operation and/or the indirect store operation. In this regard, the indirection level may be to indicate a multi-level indirection or a single level indirection. In some embodiments, the multi-level indirection includes multiple individual loads. In some embodiments, the multi-level indirection includes multiple individual stores. In some embodiments, the multi-level indirection includes a combination of one or more individual loads and one or more individual stores. The single level indirection includes an individual load or an individual store.

In some embodiments, the indirection request may include an address associated with a load store queue. The address associated with the load store queue may be included in the indirection request to return data to the load store queue at one or more op-engines of the pipeline indirection system. In some embodiments, the address of the load store queue may be sent in each indirection request to successfully return data regardless of the location of the indirection request.

In some embodiments, the indirection request may be received, from a load store queue (LSQ), at a first op-engine. The first op-engine is associated with a first data location. A data location includes a memory location in a pipeline indirection system.

The processor is to respond, using execution circuitry (e.g., pre-existing atomic execution unit at the memory interface as described herein with reference to FIGS. 11A and 11B), to the decoded single instruction by executing the decoded single instruction to access a compressed graphic list. At 305, the processor is to compute, via the first op-engine, a second data location associated with a second op-engine. In this regard, the first op-engine is to retrieve a first pointer from the first data location (e.g., the first location associated with the first op-engine). The first pointer may be utilized to determine the location of a second pointer. The processor may compute the second data location associated with the second pointer based on the location determined according to the first pointer. In turn, the processor may provide the indirection request to the second op-engine at the second data location determined.

At 307, the processor is to compute via the second op-engine, a third data location associated with a third op-engine responsive to the indirection request. The processor may retrieve the second pointer from the second data location and, in response, may compute the third data location associated with a third pointer. The processor may then provide, via the second op-engine, the indirection request to the third op-engine.

The processor is to provide, via the third op-engine, a data response to the load store queue responsive to receiving data from the third data location at 309. For example, the op-engine reads data from the third data location and sends a data response (e.g., a data acknowledgement) to the load store queue.

FIG. 4 illustrates a table showing instruction definitions for three operations according to some embodiments. As shown, the table includes the indirect load and store operations, the descriptions, and the inputs into the pipeline indirection system 100. Each of these operations are supported by one or more op-engines (e.g., the op-engine 110, 120, and 130) of the pipeline indirection system 100. The pipeline indirection system 100 may take the form of a multithreaded pipeline. In some embodiments, once a memory operation is issued, that thread is moved aside until the operation is complete. The thread may then, re-enter the pipeline advantageously removing the need to forward. In some embodiments, a multithreaded pipeline may include fencing such that indirect operations (e.g., any following operations, such as load.ind or storeack.ind) wait until the indirect operation has completed.

The LSQ 105 sends a request to an op-engine (e.g., the op-engine 110, 120, and 130) located near the list memory (e.g., the address in or at r2). The op-engine then performs a list read and dereference. In embodiments wherein the indirection level (e.g., the LEV-IND modifier) is set to 1, an indirection request may be provided to at least two data locations (e.g., next list locations such as the data location 115 and 125) which then dereferences the address of the final data location (e.g., the data location 135). In some embodiments, an indirection request (e.g., a double indirection) may include an operand such as the register r4 to support the second pointer dereferencing to the next data location. The operand r4 may provide the base value for a new data structure advantageously removing any requirement to place data structures adjacent to each other in order to reuse the same base value. When the address of the final data location is dereferenced, a data response (e.g., a data value, data acknowledgment, or a combination thereof) is returned to the LSQ 105.

If the indirection level (e.g., the LEV-IND modifier) is set to 0, a store or load (e.g., IND-LD) is provided to a data location (e.g., a dereferenced location such as the Data Location 215 and/or 225) and a data response (e.g., a data value, data acknowledgment, or a combination thereof) is returned to the LSQ 105.

FIG. 5 illustrates an example pseudo-code to execute a double-indirect load according to one embodiment as described herein. The loop is performed for each vertex v, over its neighbors. The double-indirect load is shown at line 3 as the code logprimes[labelvec[neighbors[i]]. The return value from the indirect load is t accumulated into “sum”. Written as a single machine code instruction, the double-indirect code translates as:

-   -   Load.ind ret_reg, neighbors[i], labelvec_base, logprimes_base,         SIZE=64, AM=O, OS=64, OT=U, LEV-IND=1

Ret_reg: The local register that the data will be loaded into.

Neighbors[i]: The variable from the above code segment dictating where the first ‘list’ of pointers is located.

Labelvec_base: This is an address value to perform the ‘base+offset’ address dereferencing for the first indirection.

Logprimes_base: This is an address value to perform the ‘base+offset’ address dereferencing for the second indirection.

FIG. 6 illustrates an example base+offset address format according to one embodiment as described herein. In some embodiments, data structures for sparse graphs and matrices (e.g. compressed sparse row) represent vertex or column IDs in memory as a contiguous block of integers. These integers may be used to index data structures in a non-uniform arrangement (e.g., a gather, scatter, or broadcast). In some embodiments, an op-engine (e.g., the Op-engines 110, 120, and 130) may be to interpret lists that are represented in a list of offsets format. In this regard, a base value (e.g., a 64 bit canonical address) and the address of the packed offset list may be provided as part of the operation as separate registers. The list stored in memory may then include integers that represent a count of elements. Advantageously, this allows for provision of the original IDs (e.g. vertex IDs) without scaling the IDs by the size of individual elements. In some embodiments, the integers in the list may range from a scalable floor to a scalable ceiling (e.g., the integers may be x number of bytes such as, but not limited to, 4 bytes, 8 bytes, etc.). Alternatively or additionally, the integers may be signed or unsigned.

A 32 bit unsigned integer offset value is illustrated wherein AM=O, OT=U, and OS=32 bits. The base address of the list is rSrc (r2). The conversion of the integer offset to a 64-bit address value may be performed according to the equation Dest_addr=(Offset_0*SIZE)+r3. The integer represents the distance (e.g., the distance in data elements of SIZE) from the base value r3. The location of the data element of interest is the integer offset multiplied by SIZE, and added to r3.

Detailed herein are examples of hardware, software, etc. to execute the above described instructions. For example, what is described below details aspects of instruction execution including various pipeline stages such as fetch, decode, schedule, execute, retire, etc.

Instruction Sets

An instruction set may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, location of bits) to specify, among other things, the operation to be performed (e.g., opcode) and the operand(s) on which that operation is to be performed and/or other data field(s) (e.g., mask). Some instruction formats are further broken down though the definition of instruction templates (or subformats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields (the included fields are typically in the same order, but at least some have different bit positions because there are less fields included) and/or defined to have a given field interpreted differently. Thus, each instruction of an instruction set architecture (ISA) is expressed using a given instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and includes fields for specifying the operation and the operands. For example, an exemplary ADD instruction has a specific opcode and an instruction format that includes an opcode field to specify that opcode and operand fields to select operands (source1/destination and source2); and an occurrence of this ADD instruction in an instruction stream will have specific contents in the operand fields that select specific operands.

Embodiments of the instruction(s) described herein may be embodied in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the instruction(s) may be executed on such systems, architectures, and pipelines, but are not limited to those detailed.

An instruction set may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, location of bits) to specify, among other things, the operation to be performed (e.g., opcode) and the operand(s) on which that operation is to be performed and/or other data field(s) (e.g., mask). Some instruction formats are further broken down though the definition of instruction templates (or subformats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields (the included fields are typically in the same order, but at least some have different bit positions because there are less fields included) and/or defined to have a given field interpreted differently. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and includes fields for specifying the operation and the operands. For example, an exemplary ADD instruction has a specific opcode and an instruction format that includes an opcode field to specify that opcode and operand fields to select operands (source1/destination and source2); and an occurrence of this ADD instruction in an instruction stream will have specific contents in the operand fields that select specific operands. A set of SIMD extensions referred to as the Advanced Vector Extensions (AVX) (AVX1 and AVX2) and using the Vector Extensions (VEX) coding scheme has been released and/or published (e.g., see Intel® 64 and IA-32 Architectures Software Developer's Manual, September 2014; and see Intel® Advanced Vector Extensions Programming Reference, October 2014).

Exemplary Instruction Formats

Embodiments of the instruction(s) described herein may be embodied in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the instruction(s) may be executed on such systems, architectures, and pipelines, but are not limited to those detailed.

Generic Vector Friendly Instruction Format

A vector friendly instruction format is an instruction format that is suited for vector instructions (e.g., there are certain fields specific to vector operations). While embodiments are described in which both vector and scalar operations are supported through the vector friendly instruction format, alternative embodiments use only vector operations the vector friendly instruction format.

FIGS. 12A-12B are block diagrams illustrating a generic vector friendly instruction format and instruction templates thereof according to embodiments of the invention. FIG. 7 is a block diagram illustrating a generic vector friendly instruction format and class A instruction templates thereof according to embodiments of the invention; while FIG. 8 is a block diagram illustrating the generic vector friendly instruction format and class B instruction templates thereof according to embodiments of the invention. Specifically, a generic vector friendly instruction format 800 for which are defined class A and class B instruction templates, both of which include no memory access 805 instruction templates and memory access 820 instruction templates. The term generic in the context of the vector friendly instruction format refers to the instruction format not being tied to any specific instruction set.

While embodiments of the invention will be described in which the vector friendly instruction format supports the following: a 64 byte vector operand length (or size) with 32 bit (4 byte) or 64 bit (8 byte) data element widths (or sizes) (and thus, a 64 byte vector consists of either 16 doubleword-size elements or alternatively, 8 quadword-size elements); a 64 byte vector operand length (or size) with 16 bit (2 byte) or 8 bit (1 byte) data element widths (or sizes); a 32 byte vector operand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8 bit (1 byte) data element widths (or sizes); and a 16 byte vector operand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8 bit (1 byte) data element widths (or sizes); alternative embodiments may support more, less and/or different vector operand sizes (e.g., 256 byte vector operands) with more, less, or different data element widths (e.g., 128 bit (16 byte) data element widths).

The class A instruction templates in FIG. 7 include: 1) within the no memory access 805 instruction templates there is shown a no memory access, full round control type operation 810 instruction template and a no memory access, data transform type operation 815 instruction template; and 2) within the memory access 820 instruction templates there is shown a memory access, temporal 825 instruction template and a memory access, non-temporal 830 instruction template. The class B instruction templates in FIG. 8 include: 1) within the no memory access 805 instruction templates there is shown a no memory access, write mask control, partial round control type operation 1212 instruction template and a no memory access, write mask control, vsize type operation 817 instruction template; and 2) within the memory access 820 instruction templates there is shown a memory access, write mask control 827 instruction template.

The generic vector friendly instruction format 800 includes the following fields listed below in the order illustrated in FIGS. 7-8.

Format field 840—a specific value (an instruction format identifier value) in this field uniquely identifies the vector friendly instruction format, and thus occurrences of instructions in the vector friendly instruction format in instruction streams. As such, this field is optional in the sense that it is not needed for an instruction set that has only the generic vector friendly instruction format.

Base operation field 842—its content distinguishes different base operations.

Register index field 844—its content, directly or through address generation, specifies the locations of the source and destination operands, be they in registers or in memory. These include a sufficient number of bits to select N registers from a PxQ (e.g. 32×512, 16×128, 32×1024, 64×1024) register file. While in one embodiment N may be up to three sources and one destination register, alternative embodiments may support more or less sources and destination registers (e.g., may support up to two sources where one of these sources also acts as the destination, may support up to three sources where one of these sources also acts as the destination, may support up to two sources and one destination).

Modifier field 846—its content distinguishes occurrences of instructions in the generic vector instruction format that specify memory access from those that do not; that is, between no memory access 805 instruction templates and memory access 820 instruction templates. Memory access operations read and/or write to the memory hierarchy (in some cases specifying the source and/or destination addresses using values in registers), while non-memory access operations do not (e.g., the source and destinations are registers). While in one embodiment this field also selects between three different ways to perform memory address calculations, alternative embodiments may support more, less, or different ways to perform memory address calculations.

Augmentation operation field 850—its content distinguishes which one of a variety of different operations to be performed in addition to the base operation. This field is context specific. In one embodiment of the invention, this field is divided into a class field 868, an alpha field 852, and a beta field 854. The augmentation operation field 850 allows common groups of operations to be performed in a single instruction rather than 2, 3, or 4 instructions.

Scale field 860—its content allows for the scaling of the index field's content for memory address generation (e.g., for address generation that uses 2^(scale)*index+base).

Displacement Field 862A—its content is used as part of memory address generation (e.g., for address generation that uses 2^(scale)*index+base+displacement).

Displacement Factor Field 862B (note that the juxtaposition of displacement field 862A directly over displacement factor field 862B indicates one or the other is used)—its content is used as part of address generation; it specifies a displacement factor that is to be scaled by the size of a memory access (N)—where N is the number of bytes in the memory access (e.g., for address generation that uses 2^(scale)*index+base+scaled displacement). Redundant low-order bits are ignored and hence, the displacement factor field's content is multiplied by the memory operands total size (N) in order to generate the final displacement to be used in calculating an effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field 874 (described later herein) and the data manipulation field 854C. The displacement field 862A and the displacement factor field 862B are optional in the sense that they are not used for the no memory access 805 instruction templates and/or different embodiments may implement only one or none of the two.

Data element width field 864—its content distinguishes which one of a number of data element widths is to be used (in some embodiments for all instructions; in other embodiments for only some of the instructions). This field is optional in the sense that it is not needed if only one data element width is supported and/or data element widths are supported using some aspect of the opcodes.

Write mask field 870—its content controls, on a per data element position basis, whether that data element position in the destination vector operand reflects the result of the base operation and augmentation operation. Class A instruction templates support merging-writemasking, while class B instruction templates support both merging- and zeroing-writemasking. When merging, vector masks allow any set of elements in the destination to be protected from updates during the execution of any operation (specified by the base operation and the augmentation operation); in other one embodiment, preserving the old value of each element of the destination where the corresponding mask bit has a 0. In contrast, when zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one embodiment, an element of the destination is set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (that is, the span of elements being modified, from the first to the last one); however, it is not necessary that the elements that are modified be consecutive. Thus, the write mask field 870 allows for partial vector operations, including loads, stores, arithmetic, logical, etc. While embodiments of the invention are described in which the write mask field's 870 content selects one of a number of write mask registers that contains the write mask to be used (and thus the write mask field's 870 content indirectly identifies that masking to be performed), alternative embodiments instead or additional allow the mask write field's 870 content to directly specify the masking to be performed.

Immediate field 872—its content allows for the specification of an immediate. This field is optional in the sense that is it not present in an implementation of the generic vector friendly format that does not support immediate and it is not present in instructions that do not use an immediate.

Class field 868—its content distinguishes between different classes of instructions. With reference to FIGS. 7-8, the contents of this field select between class A and class B instructions. In FIGS. 7-8, rounded corner squares are used to indicate a specific value is present in a field (e.g., class A 868A and class B 868B for the class field 868 respectively in FIGS. 7-8).

Instruction Templates of Class A

In the case of the non-memory access 805 instruction templates of class A, the alpha field 852 is interpreted as an RS field 852A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round 8852A.1 and data transform 852A.2 are respectively specified for the no memory access, round type operation 810 and the no memory access, data transform type operation 815 instruction templates), while the beta field 854 distinguishes which of the operations of the specified type is to be performed. In the no memory access 805 instruction templates, the scale field 860, the displacement field 862A, and the displacement scale filed 862B are not present.

No-Memory Access Instruction Templates—Full Round Control Type Operation

In the no memory access full round control type operation 810 instruction template, the beta field 854 is interpreted as a round control field 854A, whose content(s) provide static rounding. While in the described embodiments of the invention the round control field 854A includes a suppress all floating point exceptions (SAE) field 856 and a round operation control field 858, alternative embodiments may support may encode both these concepts into the same field or only have one or the other of these concepts/fields (e.g., may have only the round operation control field 858).

SAE field 856—its content distinguishes whether or not to disable the exception event reporting; when the SAE field's 856 content indicates suppression is enabled, a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler.

Round operation control field 858—its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest). Thus, the round operation control field 858 allows for the changing of the rounding mode on a per instruction basis. In one embodiment of the invention where a processor includes a control register for specifying rounding modes, the round operation control field's 850 content overrides that register value.

No Memory Access Instruction Templates—Data Transform Type Operation

In the no memory access data transform type operation 815 instruction template, the beta field 854 is interpreted as a data transform field 854B, whose content distinguishes which one of a number of data transforms is to be performed (e.g., no data transform, swizzle, broadcast).

In the case of a memory access 820 instruction template of class A, the alpha field 852 is interpreted as an eviction hint field 852B, whose content distinguishes which one of the eviction hints is to be used (in FIG. 7, temporal 852B.1 and non-temporal 852B.2 are respectively specified for the memory access, temporal 825 instruction template and the memory access, non-temporal 830 instruction template), while the beta field 854 is interpreted as a data manipulation field 854C, whose content distinguishes which one of a number of data manipulation operations (also known as primitives) is to be performed (e.g., no manipulation; broadcast; up conversion of a source; and down conversion of a destination). The memory access 820 instruction templates include the scale field 860, and optionally the displacement field 862A or the displacement scale field 862B.

Vector memory instructions perform vector loads from and vector stores to memory, with conversion support. As with regular vector instructions, vector memory instructions transfer data from/to memory in a data element-wise fashion, with the elements that are actually transferred is dictated by the contents of the vector mask that is selected as the write mask.

Memory Access Instruction Templates—Temporal

Temporal data is data likely to be reused soon enough to benefit from caching. This is, however, a hint, and different processors may implement it in different ways, including ignoring the hint entirely.

Memory Access Instruction Templates—Non-Temporal

Non-temporal data is data unlikely to be reused soon enough to benefit from caching in the 1st-level cache and should be given priority for eviction. This is, however, a hint, and different processors may implement it in different ways, including ignoring the hint entirely.

Instruction Templates of Class B

In the case of the instruction templates of class B, the alpha field 852 is interpreted as a write mask control (Z) field 852C, whose content distinguishes whether the write masking controlled by the write mask field 870 should be a merging or a zeroing.

In the case of the non-memory access 805 instruction templates of class B, part of the beta field 854 is interpreted as an RL field 857A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round 857A.1 and vector length (VSIZE) 857A.2 are respectively specified for the no memory access, write mask control, partial round control type operation 812 instruction template and the no memory access, write mask control, VSIZE type operation 817 instruction template), while the rest of the beta field 854 distinguishes which of the operations of the specified type is to be performed. In the no memory access 805 instruction templates, the scale field 860, the displacement field 862A, and the displacement scale filed 862B are not present.

In the no memory access, write mask control, partial round control type operation 810 instruction template, the rest of the beta field 854 is interpreted as a round operation field 859A and exception event reporting is disabled (a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler).

Round operation control field 859A—just as round operation control field 858, its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest). Thus, the round operation control field 859A allows for the changing of the rounding mode on a per instruction basis. In one embodiment of the invention where a processor includes a control register for specifying rounding modes, the round operation control field's 850 content overrides that register value.

In the no memory access, write mask control, VSIZE type operation 817 instruction template, the rest of the beta field 854 is interpreted as a vector length field 859B, whose content distinguishes which one of a number of data vector lengths is to be performed on (e.g., 128, 256, or 512 byte).

In the case of a memory access 820 instruction template of class B, part of the beta field 854 is interpreted as a broadcast field 857B, whose content distinguishes whether or not the broadcast type data manipulation operation is to be performed, while the rest of the beta field 854 is interpreted the vector length field 859B. The memory access 820 instruction templates include the scale field 860, and optionally the displacement field 862A or the displacement scale field 862B.

With regard to the generic vector friendly instruction format 800, a full opcode field 874 is shown including the format field 840, the base operation field 842, and the data element width field 864. While one embodiment is shown where the full opcode field 874 includes all of these fields, the full opcode field 874 includes less than all of these fields in embodiments that do not support all of them. The full opcode field 874 provides the operation code (opcode).

The augmentation operation field 850, the data element width field 864, and the write mask field 870 allow these features to be specified on a per instruction basis in the generic vector friendly instruction format.

The combination of write mask field and data element width field create typed instructions in that they allow the mask to be applied based on different data element widths.

The various instruction templates found within class A and class B are beneficial in different situations. In some embodiments of the invention, different processors or different cores within a processor may support only class A, only class B, or both classes. For instance, a high performance general purpose out-of-order core intended for general-purpose computing may support only class B, a core intended primarily for graphics and/or scientific (throughput) computing may support only class A, and a core intended for both may support both (of course, a core that has some mix of templates and instructions from both classes but not all templates and instructions from both classes is within the purview of the invention). Also, a single processor may include multiple cores, all of which support the same class or in which different cores support different class. For instance, in a processor with separate graphics and general purpose cores, one of the graphics cores intended primarily for graphics and/or scientific computing may support only class A, while one or more of the general purpose cores may be high performance general purpose cores with out of order execution and register renaming intended for general-purpose computing that support only class B. Another processor that does not have a separate graphics core, may include one more general purpose in-order or out-of-order cores that support both class A and class B. Of course, features from one class may also be implement in the other class in different embodiments of the invention. Programs written in a high level language would be put (e.g., just in time compiled or statically compiled) into an variety of different executable forms, including: 1) a form having only instructions of the class(es) supported by the target processor for execution; or 2) a form having alternative routines written using different combinations of the instructions of all classes and having control flow code that selects the routines to execute based on the instructions supported by the processor which is currently executing the code.

Exemplary Specific Vector Friendly Instruction Format

FIG. 9A is a block diagram illustrating an exemplary specific vector friendly instruction format according to embodiments of the invention. FIG. 9A shows a specific vector friendly instruction format 900 that is specific in the sense that it specifies the location, size, interpretation, and order of the fields, as well as values for some of those fields. The specific vector friendly instruction format 900 may be used to extend the x86 instruction set, and thus some of the fields are similar or the same as those used in the existing x86 instruction set and extension thereof (e.g., AVX). This format remains consistent with the prefix encoding field, real opcode byte field, MOD R/M field, SIB field, displacement field, and immediate fields of the existing x86 instruction set with extensions. The fields from FIG. 8 into which the fields from FIG. 9A map are illustrated.

It should be understood that, although embodiments of the invention are described with reference to the specific vector friendly instruction format 900 in the context of the generic vector friendly instruction format 800 for illustrative purposes, the invention is not limited to the specific vector friendly instruction format 900 except where claimed. For example, the generic vector friendly instruction format 800 contemplates a variety of possible sizes for the various fields, while the specific vector friendly instruction format 900 is shown as having fields of specific sizes. By way of specific example, while the data element width field 864 is illustrated as a one bit field in the specific vector friendly instruction format 900, the invention is not so limited (that is, the generic vector friendly instruction format 800 contemplates other sizes of the data element width field 864).

The generic vector friendly instruction format 800 includes the following fields listed below in the order illustrated in FIG. 9A.

EVEX Prefix (Bytes 0-3) 902—is encoded in a four-byte form.

Format Field 840 (EVEX Byte 0, bits [7:0])—the first byte (EVEX Byte 0) is the format field 840 and it contains 0x62 (the unique value used for distinguishing the vector friendly instruction format in one embodiment of the invention).

The second-fourth bytes (EVEX Bytes 1-3) include a number of bit fields providing specific capability.

REX field 905 (EVEX Byte 1, bits [7-5])—consists of a EVEX.R bit field (EVEX Byte 1, bit [7]—R), EVEX.X bit field (EVEX byte 1, bit [6]—X), and 857BEX byte 1, bit[5]—B). The EVEX.R, EVEX.X, and EVEX.B bit fields provide the same functionality as the corresponding VEX bit fields, and are encoded using is complement form, i.e. ZMM0 is encoded as 1111B, ZMM15 is encoded as 0000B. Other fields of the instructions encode the lower three bits of the register indexes as is known in the art (rrr, xxx, and bbb), so that Rrrr, Xxxx, and Bbbb may be formed by adding EVEX.R, EVEX.X, and EVEX.B.

REX′ field 810—this is the first part of the REX′ field 810 and is the EVEX.R′ bit field (EVEX Byte 1, bit [4]—R′) that is used to encode either the upper 16 or lower 16 of the extended 32 register set. In one embodiment of the invention, this bit, along with others as indicated below, is stored in bit inverted format to distinguish (in the well-known x86 32-bit mode) from the BOUND instruction, whose real opcode byte is 62, but does not accept in the MOD R/M field (described below) the value of 11 in the MOD field; alternative embodiments of the invention do not store this and the other indicated bits below in the inverted format. A value of 1 is used to encode the lower 16 registers. In other words, R′Rrrr is formed by combining EVEX.R′, EVEX.R, and the other RRR from other fields.

Opcode map field 915 (EVEX byte 1, bits [3:0]—mmmm)—its content encodes an implied leading opcode byte (0F, 0F 38, or 0F 3).

Data element width field 864 (EVEX byte 2, bit [7]—W)—is represented by the notation EVEX.W. EVEX.W is used to define the granularity (size) of the datatype (either 32-bit data elements or 64-bit data elements).

EVEX.vvvv 920 (EVEX Byte 2, bits [6:3]—vvvv)—the role of EVEX.vvvv may include the following: 1) EVEX.vvvv encodes the first source register operand, specified in inverted (1s complement) form and is valid for instructions with 2 or more source operands; 2) EVEX.vvvv encodes the destination register operand, specified in is complement form for certain vector shifts; or 3) EVEX.vvvv does not encode any operand, the field is reserved and should contain 1111b. Thus, EVEX.vvvv field 920 encodes the 4 low-order bits of the first source register specifier stored in inverted (1s complement) form. Depending on the instruction, an extra different EVEX bit field is used to extend the specifier size to 32 registers.

EVEX.U 868 Class field (EVEX byte 2, bit [2]—U)—If EVEX.U=0, it indicates class A or EVEX.U0; if EVEX.U=1, it indicates class B or EVEX.U1.

Prefix encoding field 925 (EVEX byte 2, bits [1:0]—pp)—provides additional bits for the base operation field. In addition to providing support for the legacy SSE instructions in the EVEX prefix format, this also has the benefit of compacting the SIMD prefix (rather than requiring a byte to express the SIMD prefix, the EVEX prefix requires only 2 bits). In one embodiment, to support legacy SSE instructions that use a SIMD prefix (66H, F2H, F3H) in both the legacy format and in the EVEX prefix format, these legacy SIMD prefixes are encoded into the SIMD prefix encoding field; and at runtime are expanded into the legacy SIMD prefix prior to being provided to the decoder's PLA (so the PLA can execute both the legacy and EVEX format of these legacy instructions without modification). Although newer instructions could use the EVEX prefix encoding field's content directly as an opcode extension, certain embodiments expand in a similar fashion for consistency but allow for different meanings to be specified by these legacy SIMD prefixes. An alternative embodiment may redesign the PLA to support the 2 bit SIMD prefix encodings, and thus not require the expansion.

Alpha field 852 (EVEX byte 3, bit [7]—EH; also known as EVEX.EH, EVEX.rs, EVEX.RL, EVEX.write mask control, and EVEX.N; also illustrated with α)—as previously described, this field is context specific.

Beta field 854 (EVEX byte 3, bits [6:4]—SSS, also known as EVEX.s₂₋₀, EVEX.r₂₋₀, EVEX.rr1, EVEX.LL0, EVEX.LLB; also illustrated with βββ)—as previously described, this field is context specific.

REX′ field 810—this is the remainder of the REX′ field and is the EVEX.V′ bit field (EVEX Byte 3, bit [3]—V′) that may be used to encode either the upper 16 or lower 16 of the extended 32 register set. This bit is stored in bit inverted format. A value of 1 is used to encode the lower 16 registers. In other words, V′VVVV is formed by combining EVEX.V′, EVEX.vvvv.

Write mask field 870 (EVEX byte 3, bits [2:0]—kkk)—its content specifies the index of a register in the write mask registers as previously described. In one embodiment of the invention, the specific value EVEX.kkk=000 has a special behavior implying no write mask is used for the particular instruction (this may be implemented in a variety of ways including the use of a write mask hardwired to all ones or hardware that bypasses the masking hardware).

Real Opcode Field 930 (Byte 4) is also known as the opcode byte. Part of the opcode is specified in this field.

MOD R/M Field 940 (Byte 5) includes MOD field 942, Reg field 944, and R/M field 946. As previously described, the MOD field's 942 content distinguishes between memory access and non-memory access operations. The role of Reg field 944 can be summarized to two situations: encoding either the destination register operand or a source register operand, or be treated as an opcode extension and not used to encode any instruction operand. The role of R/M field 946 may include the following: encoding the instruction operand that references a memory address, or encoding either the destination register operand or a source register operand.

Scale, Index, Base (SIB) Byte (Byte 6)—As previously described, the scale field's 850 content is used for memory address generation. SIB.xxx 954 and SIB.bbb 956—the contents of these fields have been previously referred to with regard to the register indexes Xxxx and Bbbb.

Displacement field 862A (Bytes 7-10)—when MOD field 942 contains 10, bytes 7-10 are the displacement field 862A, and it works the same as the legacy 32-bit displacement (disp32) and works at byte granularity.

Displacement factor field 862B (Byte 7)—when MOD field 942 contains 01, byte 7 is the displacement factor field 862B. The location of this field is that same as that of the legacy x86 instruction set 8-bit displacement (disp8), which works at byte granularity. Since disp8 is sign extended, it can only address between −128 and 127 bytes offsets; in terms of 64 byte cache lines, disp8 uses 8 bits that can be set to only four really useful values −128, −64, 0, and 64; since a greater range is often needed, disp32 is used; however, disp32 requires 4 bytes. In contrast to disp8 and disp32, the displacement factor field 862B is a reinterpretation of disp8; when using displacement factor field 862B, the actual displacement is determined by the content of the displacement factor field multiplied by the size of the memory operand access (N). This type of displacement is referred to as disp8*N. This reduces the average instruction length (a single byte of used for the displacement but with a much greater range). Such compressed displacement is based on the assumption that the effective displacement is multiple of the granularity of the memory access, and hence, the redundant low-order bits of the address offset do not need to be encoded. In other words, the displacement factor field 862B substitutes the legacy x86 instruction set 8-bit displacement. Thus, the displacement factor field 862B is encoded the same way as an x86 instruction set 8-bit displacement (so no changes in the Mod RM/SIB encoding rules) with the only exception that disp8 is overloaded to disp8*N. In other words, there are no changes in the encoding rules or encoding lengths but only in the interpretation of the displacement value by hardware (which needs to scale the displacement by the size of the memory operand to obtain a byte-wise address offset). Immediate field 872 operates as previously described.

Full Opcode Field

FIG. 9B is a block diagram illustrating the fields of the specific vector friendly instruction format 900 that make up the full opcode field 874 according to one embodiment of the invention. Specifically, the full opcode field 874 includes the format field 840, the base operation field 842, and the data element width (W) field 864. The base operation field 842 includes the prefix encoding field 925, the opcode map field 915, and the real opcode field 930.

Register Index Field

FIG. 9C is a block diagram illustrating the fields of the specific vector friendly instruction format 900 that make up the register index field 844 according to one embodiment of the invention. Specifically, the register index field 844 includes the REX field 905, the REX′ field 910, the MODR/M.reg field 944, the MODR/M.r/m field 946, the VVVV field 920, xxx field 954, and the bbb field 956.

Augmentation Operation Field

FIG. 9D is a block diagram illustrating the fields of the specific vector friendly instruction format 900 that make up the augmentation operation field 850 according to one embodiment of the invention. When the class (U) field 868 contains 0, it signifies EVEX.U0 (class A 868A); when it contains 1, it signifies EVEX.U1 (class B 868B). When U=0 and the MOD field 942 contains 11 (signifying a no memory access operation), the alpha field 852 (EVEX byte 3, bit [7]—EH) is interpreted as the rs field 852A. When the rs field 852A contains a 1 (round 852A.1), the beta field 854 (EVEX byte 3, bits [6:4]—SSS) is interpreted as the round control field 854A. The round control field 854A includes a one bit SAE field 856 and a two bit round operation field 858. When the rs field 852A contains a 0 (data transform 852A.2), the beta field 854 (EVEX byte 3, bits [6:4]—SSS) is interpreted as a three bit data transform field 854B. When U=0 and the MOD field 942 contains 00, 01, or 10 (signifying a memory access operation), the alpha field 852 (EVEX byte 3, bit [7]—EH) is interpreted as the eviction hint (EH) field 852B and the beta field 854 (EVEX byte 3, bits [6:4]—SSS) is interpreted as a three bit data manipulation field 854C.

When U=1, the alpha field 852 (EVEX byte 3, bit [7]—EH) is interpreted as the write mask control (Z) field 852C. When U=1 and the MOD field 942 contains 11 (signifying a no memory access operation), part of the beta field 854 (EVEX byte 3, bit [4]—S₀) is interpreted as the RL field 857A; when it contains a 1 (round 857A.1) the rest of the beta field 854 (EVEX byte 3, bit [6-5]—S₂₄) is interpreted as the round operation field 859A, while when the RL field 857A contains a 0 (VSIZE 857.A2) the rest of the beta field 854 (EVEX byte 3, bit [6-5]—S₂₋₁) is interpreted as the vector length field 859B (EVEX byte 3, bit [6-5]—L₁₋₀). When U=1 and the MOD field 942 contains 00, 01, or 10 (signifying a memory access operation), the beta field 854 (EVEX byte 3, bits [6:4]—SSS) is interpreted as the vector length field 859B (EVEX byte 3, bit [6-5]—L₁₋₀) and the broadcast field 857B (EVEX byte 3, bit [4]—B).

Exemplary Register Architecture

FIG. 10 is a block diagram of a register architecture 1000 according to one embodiment of the invention. In the embodiment illustrated, there are 32 vector registers 1010 that are 58 bits wide; these registers are referenced as zmm0 through zmm31. The lower order 256 bits of the lower 16 zmm registers are overlaid on registers ymm0-16. The lower order 128 bits of the lower 16 zmm registers (the lower order 128 bits of the ymm registers) are overlaid on registers xmm0-15. The specific vector friendly instruction format 1300 operates on these overlaid register file as illustrated in the below tables.

Adjustable Vector Length Class Operations Registers Instruction Templates A (FIG. 810, 815, zmm registers (the vector that do not include the 7; U = 0) 825, 830 length is 64 byte) vector length field B (FIG. 88 zmm registers (the vector 859B 8; U = 1) length is 64 byte) Instruction templates B (FIG. 817, 827 zmm, ymm, or xmm that do include the 8; U = 1) registers (the vector vector length field length is 64 byte, 32 859B byte, or 16 byte) depending on the vector length field 859B

In other words, the vector length field 859B selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the preceding length; and instructions templates without the vector length field 859B operate on the maximum vector length. Further, in one embodiment, the class B instruction templates of the specific vector friendly instruction format 1300 operate on packed or scalar single/double-precision floating point data and packed or scalar integer data. Scalar operations are operations performed on the lowest order data element position in an zmm/ymm/xmm register; the higher order data element positions are either left the same as they were prior to the instruction or zeroed depending on the embodiment.

Write mask registers 1015—in the embodiment illustrated, there are 8 write mask registers (k0 through k7), each 64 bits in size. In an alternate embodiment, the write mask registers 1015 are 16 bits in size. As previously described, in one embodiment of the invention, the vector mask register k0 cannot be used as a write mask; when the encoding that would normally indicate k0 is used for a write mask, it selects a hardwired write mask of 0xFFFF, effectively disabling write masking for that instruction.

General-purpose registers 1025—in the embodiment illustrated, there are sixteen 64-bit general-purpose registers that are used along with the existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

Scalar floating point stack register file (x87 stack) 1045, on which is aliased the MMX packed integer flat register file 1050—in the embodiment illustrated, the x87 stack is an eight-element stack used to perform scalar floating-point operations on 32/64/80-bit floating point data using the x87 instruction set extension; while the MMX registers are used to perform operations on 64-bit packed integer data, as well as to hold operands for some operations performed between the MMX and XMM registers.

Alternative embodiments of the invention may use wider or narrower registers. Additionally, alternative embodiments of the invention may use more, less, or different register files and registers.

Exemplary Core Architectures, Processors, and Computer Architectures

Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: 1) a general purpose in-order core intended for general-purpose computing; 2) a high performance general purpose out-of-order core intended for general-purpose computing; 3) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput). Such different processors lead to different computer system architectures, which may include: 1) the coprocessor on a separate chip from the CPU; 2) the coprocessor on a separate die in the same package as a CPU; 3) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and 4) a system on a chip that may include on the same die the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures.

Exemplary Core Architectures

In-Order and Out-of-Order Core Block Diagram

FIG. 11A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments of the invention. FIG. 11B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments of the invention. The solid lined boxes in FIGS. 11A-B illustrate the in-order pipeline and in-order core, while the optional addition of the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline and core. Given that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

In FIG. 11A, a processor pipeline 1100 includes a fetch stage 1102, a length decode stage 1104, a decode stage 1106, an allocation stage 1108, a renaming stage 1110, a scheduling (also known as a dispatch or issue) stage 1512, a register read/memory read stage 1114, an execute stage 1112, a write back/memory write stage 1118, an exception handling stage 1122, and a commit stage 1124.

FIG. 11B shows processor core 1190 including a front end unit 1130 coupled to an execution engine unit 1150, and both are coupled to a memory unit 1130. The core 1190 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core 1190 may be a special-purpose core, such as, for example, a network or communication core, compression engine, coprocessor core, general purpose computing graphics processing unit (GPGPU) core, graphics core, or the like.

The front end unit 1130 includes a branch prediction unit 1132 coupled to an instruction cache unit 1134, which is coupled to an instruction translation lookaside buffer (TLB) 1136, which is coupled to an instruction fetch unit 1138, which is coupled to a decode unit 1140. The decode unit 1140 (or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit 1140 may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one embodiment, the core 1190 includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in decode unit 1140 or otherwise within the front end unit 1130). The decode unit 1140 is coupled to a rename/allocator unit 1152 in the execution engine unit 1150.

The execution engine unit 1150 includes the rename/allocator unit 1152 coupled to a retirement unit 1154 and a set of one or more scheduler unit(s) 1156. The scheduler unit(s) 1156 represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s) 1156 is coupled to the physical register file(s) unit(s) 1158. Each of the physical register file(s) units 1158 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit 1158 comprises a vector registers unit, a write mask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s) 1158 is overlapped by the retirement unit 1154 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit 1154 and the physical register file(s) unit(s) 1158 are coupled to the execution cluster(s) 1120. The execution cluster(s) 1120 includes a set of one or more execution units 1122 and a set of one or more memory access units 1124. The execution units 1122 may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s) 1156, physical register file(s) unit(s) 1158, and execution cluster(s) 1120 are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster—and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s) 1124). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units 1124 is coupled to the memory unit 1130, which includes a data TLB unit 1132 coupled to a data cache unit 1134 coupled to a level 2 (L2) cache unit 1136. In one exemplary embodiment, the memory access units 1124 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 1132 in the memory unit 1130. The instruction cache unit 1134 is further coupled to a level 2 (L2) cache unit 1136 in the memory unit 1130. The L2 cache unit 1136 is coupled to one or more other levels of cache and eventually to a main memory.

By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline 1100 as follows: 1) the instruction fetch 1138 performs the fetch and length decoding stages 1102 and 1104; 2) the decode unit 1140 performs the decode stage 1106; 3) the rename/allocator unit 1152 performs the allocation stage 1108 and renaming stage 1110; 4) the scheduler unit(s) 1156 performs the schedule stage 1512; 5) the physical register file(s) unit(s) 1158 and the memory unit 1130 perform the register read/memory read stage 1114; the execution cluster 1120 perform the execute stage 1112; 6) the memory unit 1130 and the physical register file(s) unit(s) 1158 perform the write back/memory write stage 1118; 7) various units may be involved in the exception handling stage 1122; and 8) the retirement unit 1154 and the physical register file(s) unit(s) 1158 perform the commit stage 1124.

The core 1190 may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif.; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, Calif.), including the instruction(s) described herein. In one embodiment, the core 1190 includes logic to support a packed data instruction set extension (e.g., AVX1, AVX2), thereby allowing the operations used by many multimedia applications to be performed using packed data.

It should be understood that the core may support multithreading (executing two or more parallel sets of operations or threads), and may do so in a variety of ways including time sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that physical core is simultaneously multithreading), or a combination thereof (e.g., time sliced fetching and decoding and simultaneous multithreading thereafter such as in the Intel® Hyperthreading technology).

While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor also includes separate instruction and data cache units 1134/1134 and a shared L2 cache unit 1136, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor. Alternatively, all of the cache may be external to the core and/or the processor.

Specific Exemplary in-Order Core Architecture

FIGS. 12A-B illustrate a block diagram of a more specific exemplary in-order core architecture, which core would be one of several logic blocks (including other cores of the same type and/or different types) in a chip. The logic blocks communicate through a high-bandwidth interconnect network (e.g., a ring network) with some fixed function logic, memory I/O interfaces, and other necessary I/O logic, depending on the application.

FIG. 12A is a block diagram of a single processor core, along with its connection to the on-die interconnect network 1202 and with its local subset of the Level 2 (L2) cache 1204, according to embodiments of the invention. In one embodiment, an instruction decoder 1200 supports the x86 instruction set with a packed data instruction set extension. An L1 cache 1206 allows low-latency accesses to cache memory into the scalar and vector units. While in one embodiment (to simplify the design), a scalar unit 1208 and a vector unit 1210 use separate register sets (respectively, scalar registers 1212 and vector registers 1214) and data transferred between them is written to memory and then read back in from a level 1 (L1) cache 1206, alternative embodiments of the invention may use a different approach (e.g., use a single register set or include a communication path that allow data to be transferred between the two register files without being written and read back).

The local subset of the L2 cache 1204 is part of a global L2 cache that is divided into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of the L2 cache 1204. Data read by a processor core is stored in its L2 cache subset 1204 and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 1204 and is flushed from other subsets, if necessary. The ring network ensures coherency for shared data. The ring network is bi-directional to allow agents such as processor cores, L2 caches and other logic blocks to communicate with each other within the chip. Each ring data-path is 1012-bits wide per direction.

FIG. 12B is an expanded view of part of the processor core in FIG. 12A according to embodiments of the invention. FIG. 12B includes an L1 data cache 1206A part of the L1 cache 1204, as well as more detail regarding the vector unit 1210 and the vector registers 1214. Specifically, the vector unit 1210 is a 12-wide vector processing unit (VPU) (see the 12-wide ALU 1228), which executes one or more of integer, single-precision float, and double-precision float instructions. The VPU supports swizzling the register inputs with swizzle unit 1220, numeric conversion with numeric convert units 1222A-B, and replication with replication unit 1224 on the memory input. Write mask registers 1226 allow predicating resulting vector writes.

FIG. 13 is a block diagram of a processor 1300 that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to embodiments of the invention. The solid lined boxes in FIG. 13 illustrate a processor 1300 with a single core 1302A, a system agent 1310, a set of one or more bus controller units 1312, while the optional addition of the dashed lined boxes illustrates an alternative processor 1300 with multiple cores 1302A-N, a set of one or more integrated memory controller unit(s) 1314 in the system agent unit 1310, and special purpose logic 1308.

Thus, different implementations of the processor 1300 may include: 1) a CPU with the special purpose logic 1308 being integrated graphics and/or scientific (throughput) logic (which may include one or more cores), and the cores 1302A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); 2) a coprocessor with the cores 1302A-N being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and 3) a coprocessor with the cores 1302A-N being a large number of general purpose in-order cores. Thus, the processor 1300 may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor 1300 may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units 1306, and external memory (not shown) coupled to the set of integrated memory controller units 1314. The set of shared cache units 1306 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit 1312 interconnects the integrated graphics logic 1308 (integrated graphics logic 1308 is an example of and is also referred to herein as special purpose logic), the set of shared cache units 1306, and the system agent unit 1310/integrated memory controller unit(s) 1314, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units 1306 and cores 1302-A-N.

In some embodiments, one or more of the cores 1302A-N are capable of multi-threading. The system agent 1310 includes those components coordinating and operating cores 1302A-N. The system agent unit 1310 may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores 1302A-N and the integrated graphics logic 1308. The display unit is for driving one or more externally connected displays.

The cores 1302A-N may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores 1302A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.

Exemplary Computer Architectures

FIGS. 14-17 are block diagrams of exemplary computer architectures. Other system designs and configurations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable. In general, a huge variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.

Referring now to FIG. 14, shown is a block diagram of a system 1400 in accordance with one embodiment of the present invention. The system 1400 may include one or more processors 1410, 1415, which are coupled to a controller hub 1420. In one embodiment the controller hub 1420 includes a graphics memory controller hub (GMCH) 1490 and an Input/Output Hub (IOH) 1450 (which may be on separate chips); the GMCH 1490 includes memory and graphics controllers to which are coupled memory 1440 and a coprocessor 1445; the IOH 1450 couples input/output (I/O) devices 1460 to the GMCH 1490. Alternatively, one or both of the memory and graphics controllers are integrated within the processor (as described herein), the memory 1440 and the coprocessor 1445 are coupled directly to the processor 1410, and the controller hub 1420 in a single chip with the IOH 1450.

The optional nature of additional processors 1415 is denoted in FIG. 14 with broken lines. Each processor 1410, 1415 may include one or more of the processing cores described herein and may be some version of the processor 1300.

The memory 1440 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub 1420 communicates with the processor(s) 1410, 1415 via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as QuickPath Interconnect (QPI), or similar connection 1495.

In one embodiment, the coprocessor 1445 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub 1420 may include an integrated graphics accelerator.

There can be a variety of differences between the physical resources 1410, 1415 in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like.

In one embodiment, the processor 1410 executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor 1410 recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor 1445. Accordingly, the processor 1410 issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor 1445. Coprocessor(s) 1445 accept and execute the received coprocessor instructions.

Referring now to FIG. 15, shown is a block diagram of a first more specific exemplary system 1500 in accordance with an embodiment of the present invention. As shown in FIG. 15, multiprocessor system 1500 is a point-to-point interconnect system, and includes a first processor 1570 and a second processor 1580 coupled via a point-to-point interconnect 1550. Each of processors 1570 and 1580 may be some version of the processor 1300. In one embodiment of the invention, processors 1570 and 1580 are respectively processors 1410 and 1415, while coprocessor 1538 is coprocessor 1445. In another embodiment, processors 1570 and 1580 are respectively processor 1410 coprocessor 1445.

Processors 1570 and 1580 are shown including integrated memory controller (IMC) units 1572 and 1582, respectively. Processor 1570 also includes as part of its bus controller units point-to-point (P-P) interfaces 1576 and 1578; similarly, second processor 1580 includes P-P interfaces 1586 and 1588. Processors 1570, 1580 may exchange information via a point-to-point (P-P) interface 1550 using P-P interface circuits 1578, 1588. As shown in FIG. 15, IMCs 1572 and 1582 couple the processors to respective memories, namely a memory 1532 and a memory 1534, which may be portions of main memory locally attached to the respective processors.

Processors 1570, 1580 may each exchange information with a chipset 1590 via individual P-P interfaces 1552, 1554 using point to point interface circuits 1576, 1594, 1586, 1598. Chipset 1590 may optionally exchange information with the coprocessor 1538 via a high-performance interface 1592. In one embodiment, the coprocessor 1538 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.

A shared cache (not shown) may be included in either processor or outside of both processors, yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.

Chipset 1590 may be coupled to a first bus 1516 via an interface 1596. In one embodiment, first bus 1516 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present invention is not so limited.

As shown in FIG. 15, various I/O devices 1514 may be coupled to first bus 1516, along with a bus bridge 1514 which couples first bus 1516 to a second bus 1520. In one embodiment, one or more additional processor(s) 1515, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor, are coupled to first bus 1516. In one embodiment, second bus 1516 may be a low pin count (LPC) bus. Various devices may be coupled to a second bus 1516 including, for example, a keyboard and/or mouse 1518, communication devices 1527 and a storage unit 1528 such as a disk drive or other mass storage device which may include instructions/code and data 1530, in one embodiment. Further, an audio I/O 1524 may be coupled to the second bus 1516. Note that other architectures are possible. For example, instead of the point-to-point architecture of FIG. 15, a system may implement a multi-drop bus or other such architecture.

Referring now to FIG. 16, shown is a block diagram of a second more specific exemplary system 1600 in accordance with an embodiment of the present invention. Like elements in FIGS. 15 and 16 bear like reference numerals, and certain aspects of FIG. 15 have been omitted from FIG. 16 in order to avoid obscuring other aspects of FIG. 16.

FIG. 16 illustrates that the processors 1570, 1580 may include integrated memory and I/O control logic (“CL”) 1572 and 1582, respectively. Thus, the CL 1572, 1582 include integrated memory controller units and include I/O control logic. FIG. 16 illustrates that not only are the memories 1532, 1534 coupled to the CL 1572, 1582, but also that I/O devices 1614 are also coupled to the control logic 1572, 1582. Legacy I/O devices 1615 are coupled to the chipset 1590.

Referring now to FIG. 17, shown is a block diagram of a SoC 1700 in accordance with an embodiment of the present invention. Similar elements in FIG. 13 bear like reference numerals. Also, dashed lined boxes are optional features on more advanced SoCs. In FIG. 17, an interconnect unit(s) 1702 is coupled to: an application processor 1710 which includes a set of one or more cores 1302A-N, which include cache units 1304A-N, and shared cache unit(s) 1306; a system agent unit 1310; a bus controller unit(s) 1316; an integrated memory controller unit(s) 1314; a set or one or more coprocessors 1716 which may include integrated graphics logic, an image processor, an audio processor, and a video processor; an static random access memory (SRAM) unit 1730; a direct memory access (DMA) unit 1732; and a display unit 1740 for coupling to one or more external displays. In one embodiment, the coprocessor(s) 1720 include a special-purpose processor, such as, for example, a network or communication processor, compression engine, GPGPU, a high-throughput MIC processor, embedded processor, or the like.

Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the invention may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

Program code, such as code 1530 illustrated in FIG. 15, may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices, in known fashion. For purposes of this application, a processing system includes any system that has a processor, such as, for example; a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

The program code may be implemented in a high level procedural or object oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.

One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as “IP cores” may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.

Such machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritable's (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), phase change memory (PCM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.

Accordingly, embodiments of the invention also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.

Emulation (Including Binary Translation, Code Morphing, Etc.)

In some cases, an instruction converter may be used to convert an instruction from a source instruction set to a target instruction set. For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert an instruction to one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on processor, off processor, or part on and part off processor.

FIG. 14 is a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. FIG. 14 shows a program in a high level language 1762 may be compiled using an x86 compiler 1764 to generate x86 binary code 1766 that may be natively executed by a processor with at least one x86 instruction set core 1776. The processor with at least one x86 instruction set core 1776 represents any processor that can perform substantially the same functions as an Intel processor with at least one x86 instruction set core by compatibly executing or otherwise processing (1) a substantial portion of the instruction set of the Intel x86 instruction set core or (2) object code versions of applications or other software targeted to run on an Intel processor with at least one x86 instruction set core, in order to achieve substantially the same result as an Intel processor with at least one x86 instruction set core. The x86 compiler 1764 represents a compiler that is operable to generate x86 binary code 1766 (e.g., object code) that can, with or without additional linkage processing, be executed on the processor with at least one x86 instruction set core 1776. Similarly, FIG. 14 shows the program in the high level language 1762 may be compiled using an alternative instruction set compiler 1768 to generate alternative instruction set binary code 1770 that may be natively executed by a processor without at least one x86 instruction set core 1774 (e.g., a processor with cores that execute the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif. and/or that execute the ARM instruction set of ARM Holdings of Sunnyvale, Calif.). The instruction converter 1772 is used to convert the x86 binary code 1766 into code that may be natively executed by the processor without an x86 instruction set core 1774. This converted code is not likely to be the same as the alternative instruction set binary code 1770 because an instruction converter capable of this is difficult to make; however, the converted code will accomplish the general operation and be made up of instructions from the alternative instruction set. Thus, the instruction converter 1772 represents software, firmware, hardware, or a combination thereof that, through emulation, simulation or any other process, allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code 1766.

Further Examples

Example 1. A processor comprising: fetch circuitry to fetch a single instruction to access a compressed graphic list; decode circuitry to decode the fetched single instruction; and execution circuitry to execute the decoded single instruction to cause access to the compressed graphic list by: receiving, from a load store queue, at a first op-engine associated with a first data location, an indirection request; computing, via the first op-engine, a second data location associated with a second op-engine; computing, via the second op-engine, a third data location associated with a third op-engine responsive to the indirection request; and providing, via the third op-engine, a data response to the load store queue responsive to receiving data from the third data location.

Example 2. The processor of example 1, wherein the single instruction comprises at least one of a list load, pointer deference, an indirect load operation, or an indirect store operation.

Example 3. The processor of example 1, wherein the first op-engine is to: retrieve a first pointer from the first data location; and compute the second data location associated with a second pointer.

Example 4. The processor of example 3, wherein the second op-engine is to: retrieve the second pointer from the second data location; and compute the third data location associated with a third pointer.

Example 5. The processor of example 1, wherein a data location comprises a emory location in a pipeline indirection system.

Example 6. The processor of example 1, wherein the indirection request comprises at least one of a multi-indirection or a single indirection.

Example 7. The processor of example 1, wherein the indirection request comprises an indirect operation, and wherein the indirect operation comprises an indirect load operation or an indirect store operation.

Example 8. The processor of example 7, further comprising determining a level of indirection for the indirect load operation or the indirect store operation.

Example 9. The processor of example 1, wherein the data response comprises at least one of a data value or a data acknowledgement.

Example 10. The processor of example 1, wherein the indirection request comprises an address associated with the load store queue, and wherein the address associated with the load store queue is sent in the indirection request to return data to the load store queue at one or more op-engines of the pipeline indirection system.

Example 11. A method comprising: fetching and decoding, using fetch and decode circuitry, a single instruction to access a compressed graphic list; and responding, using execution circuitry, to the decoded instruction by receiving, from a load store queue, at a first op-engine associated with a first data location, an indirection request; determining, via the first op-engine, a second data location associated with a second op-engine; determining, via the second op-engine, a third data location associated with a third op-engine responsive to the indirection request; and providing, via the third op-engine, a data response to the load store queue responsive to receiving data from the third data location.

Example 12. The method of example 11, wherein the single instruction comprises at least one of a list load, pointer deference, an indirect load operation, or an indirect store operation.

Example 13. The method of example 11, wherein the first op-engine is to: retrieve a first pointer from the first data location; and compute the second data location associated with a second pointer.

Example 14. The method of example 11, wherein the second op-engine is to: retrieve the second pointer from the second data location; and compute the third data location associated with a third pointer.

Example 15. The method of example 11, wherein the indirection request comprises an indirection level, and wherein the indirection level is to indicate a multi-level indirection.

Example 16. The method of example 11, wherein the indirection request comprises an indirect operation, and wherein the indirect operation comprises an indirect load operation or an indirect store operation.

Example 17. The method of example 11, wherein the data response comprises a data value.

Example 18. The method of example 11, wherein the indirection request comprises an address associated with the load store queue, and wherein the address associated with the load store queue is sent in the indirection request to return data to the load store queue at one or more op-engines of the pipeline indirection system.

Example 19. A system comprising: a memory; and a processor comprising: fetch circuitry to fetch a single instruction to access a compressed graphic list; decode circuitry to decode the fetched single instruction; and execution circuitry to execute the decoded single instruction to cause access to the compressed graphic list by: receiving, from a load store queue, at a first op-engine associated with a first data location, an indirection request; computing, via the first op-engine, a second data location associated with a second op-engine; computing, via the second op-engine, a third data location associated with a third op-engine responsive to the indirection request; and providing, via the third op-engine, a data response to the load store queue responsive to receiving data from the third data location.

Example 20. The system of example 19, wherein the data response comprises at least one of a data value or a data acknowledgement. 

What is claimed is:
 1. A processor comprising: fetch circuitry to fetch a single instruction to access a compressed graphic list; decode circuitry to decode the fetched single instruction; and execution circuitry to execute the decoded single instruction to cause access to the compressed graphic list by: receiving, from a load store queue, at a first op-engine associated with a first data location, an indirection request; computing, via the first op-engine, a second data location associated with a second op-engine; computing, via the second op-engine, a third data location associated with a third op-engine responsive to the indirection request; and providing, via the third op-engine, a data response to the load store queue responsive to receiving data from the third data location.
 2. The processor of claim 1, wherein the single instruction comprises at least one of a list load, pointer deference, an indirect load operation, or an indirect store operation.
 3. The processor of claim 1, wherein the first op-engine is to: retrieve a first pointer from the first data location; and compute the second data location associated with a second pointer.
 4. The processor of claim 3, wherein the second op-engine is to: retrieve the second pointer from the second data location; and compute the third data location associated with a third pointer.
 5. The processor of claim 1, wherein a data location comprises a memory location in a pipeline indirection system.
 6. The processor of claim 1, wherein the indirection request comprises at least one of a multi-indirection or a single indirection.
 7. The processor of claim 1, wherein the indirection request comprises an indirect operation, and wherein the indirect operation comprises an indirect load operation or an indirect store operation.
 8. The processor of claim 7, further comprising determining a level of indirection for the indirect load operation or the indirect store operation.
 9. The processor of claim 1, wherein the data response comprises at least one of a data value or a data acknowledgement.
 10. The processor of claim 1, wherein the indirection request comprises an address associated with the load store queue, and wherein the address associated with the load store queue is sent in the indirection request to return data to the load store queue at one or more op-engines of the pipeline indirection system.
 11. A method comprising: fetching and decoding, using fetch and decode circuitry, a single instruction to access a compressed graphic list; and responding, using execution circuitry, to the decoded instruction by receiving, from a load store queue, at a first op-engine associated with a first data location, an indirection request; determining, via the first op-engine, a second data location associated with a second op-engine; determining, via the second op-engine, a third data location associated with a third op-engine responsive to the indirection request; and providing, via the third op-engine, a data response to the load store queue responsive to receiving data from the third data location.
 12. The method of claim 11, wherein the single instruction comprises at least one of a list load, pointer deference, an indirect load operation, or an indirect store operation.
 13. The method of claim 11, wherein the first op-engine is to: retrieve a first pointer from the first data location; and compute the second data location associated with a second pointer.
 14. The method of claim 11, wherein the second op-engine is to: retrieve the second pointer from the second data location; and compute the third data location associated with a third pointer.
 15. The method of claim 11, wherein the indirection request comprises an indirection level, and wherein the indirection level is to indicate a multi-level indirection.
 16. The method of claim 11, wherein the indirection request comprises an indirect operation, and wherein the indirect operation comprises an indirect load operation or an indirect store operation.
 17. The method of claim 11, wherein the data response comprises a data value.
 18. The method of claim 11, wherein the indirection request comprises an address associated with the load store queue, and wherein the address associated with the load store queue is sent in the indirection request to return data to the load store queue at one or more op-engines of the pipeline indirection system.
 19. A system comprising: a memory; and a processor comprising: fetch circuitry to fetch a single instruction to access a compressed graphic list; decode circuitry to decode the fetched single instruction; and execution circuitry to execute the decoded single instruction to cause access to the compressed graphic list by: receiving, from a load store queue, at a first op-engine associated with a first data location, an indirection request; computing, via the first op-engine, a second data location associated with a second op-engine; computing, via the second op-engine, a third data location associated with a third op-engine responsive to the indirection request; and providing, via the third op-engine, a data response to the load store queue responsive to receiving data from the third data location.
 20. The system of claim 19, wherein the data response comprises at least one of a data value or a data acknowledgement. 